1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly, it relates to the structure of a memory cell of a static semiconductor memory device (SRAM: static random access memory) comprising memory cells (hereinafter referred to as xe2x80x9cfull CMOS cellsxe2x80x9d) each including six MOS (metal oxide semiconductor) transistors.
2. Description of the Background Art
FIG. 11 shows an exemplary structure of a memory cell 1 of a conventional SRAM. For the convenience of illustration, FIG. 11 shows only polysilicon wires 3a to 3e forming gates of MOS transistors without showing wires located above the polysilicon wires 3a to 3e. 
As shown in FIG. 11, the memory cell 1 includes six MOS transistors Q1 to Q6. More specifically, the memory cell 1 includes first and second driver nMOS transistors Q1 and Q2, first and second load pMOS transistors Q3 and Q4 and first and second access nMOS transistors Q5 and Q6.
The first driver nMOS transistor Q1 is formed on the intersection between an active region 2a and the polysilicon wire 3b, the second driver nMOS transistor Q2 is formed on the intersection between an active region 2d and the polysilicon wire 3c, the first load pMOS transistor Q3 is formed on the intersection between an active region 2b and the polysilicon wire 3b, the second load pMOS transistor Q4 is formed on the intersection between an active region 2c and the polysilicon wire 3c, the first access nMOS transistor Q5 is formed on the intersection between the active region 2a and the polysilicon wire 3a, and the second access nMOS transistor Q6 is formed on the intersection between the active region 2d and the polysilicon wire 3d. 
A large number of memory cells 1 having the aforementioned structure are so arranged as to form a memory cell array 4, as shown in FIG. 12. Referring to FIG. 11, active regions 2f and 2e and a polysilicon wire 3e belong to other memory cells 1 adjacent to this memory cell 11 respectively.
When a power supply voltage is increased, a memory cell current is increased to subsequently increase a ground potential GND of the memory cell 1. Therefore, the operating margin of the SRAM is disadvantageously reduced.
In order to prevent such inconvenience, the gate width WA of the access nMOS transistors Q5 and Q6 is reduced below the gate width WD of the driver nMOS transistors Q1 and Q2 thereby reducing the current. More specifically, narrow potions 16a to 16c are provided on the active regions 2a, 2d and 2e respectively while the gate width WA of the first and second access nMOS transistors Q5 and Q6 is reduced below the gate width WD of the first and second driver nMOS transistors Q1 and Q2 as shown in FIG. 11.
On the other hand, Japanese Patent Laying-Open No. 63-100771 (1988), for example, describes a static memory including transfer transistors and driver transistors having substantially identical gate widths. In the static memory described in this gazette, however, each diffusion layer itself has a complicated structure.
When the active regions 2a, 2d and 2e are provided with the narrow portions 16a to 16c respectively as described above, the shapes thereof are complicated. This results in the following problem:
In order to form the active regions 2a to 2f, resist patterns having shapes corresponding to those of the active regions 2a to 2f are generally formed by photolithography for performing prescribed processing with the resist patterns. When the active regions 2a, 2d and 2e have complicated shapes as described above, however, resolution in formation of the resist patterns is so reduced by light interference or the like that it is difficult to form the resist patterns in desired shapes. Therefore, the shapes of the active regions 2a, 2d, 2e etc. formed through these resist patterns are also dispersed. Consequently, no desired device characteristics are attained but the reliability of the SRAM is disadvantageously reduced.
Particularly the narrow portions 16a to 16c smaller in width than the remaining portions of the active regions 2a, 2d and 2e are remarkably influenced by fluctuation of the width. This leads to remarkable fluctuation of the gate width WA of the access nMOS transistors Q5 and Q6 and remarkable dispersion of the characteristics of the access nMOS transistors Q5 and Q6. Thus, the performance of the SRAM is disadvantageously reduced.
The aforementioned problem conceivably further remarkably arises as the memory cell 1 of the SRAM is refined. When the active regions 2a to 2f have simple shapes such as linear shapes as shown in FIG. 11, the widths of the remaining portions of the active regions 2a to 2f other than the aforementioned narrow portions 16a to 16c are conceivably less remarkably fluctuated, conceivably leading to significant influence exerted on the device characteristics by fluctuation of the widths of the narrow portions 16a to 16c. 
Accordingly, an object of the present invention is to provide a static semiconductor memory device exhibiting high performance and high reliability also when the same is refined.
The static semiconductor memory device according to the present invention comprises a memory cell including an access MOS (metal oxide semiconductor) transistor, a driver MOS transistor and a load MOS transistor, a first wire forming the gate of the access MOS transistor and a second wire extending in the same direction as the first wire for forming the gate of the driver MOS transistor and the gate of the load MOS transistor. The gate width of the access MOS transistor and that of the driver MOS transistor are equalized with each other.
When the gate width of the access MOS transistor and that of the driver MOS transistor are equalized with each other, no narrow portion may be provided on an active region including source and drain regions of the access MOS transistor and the driver MOS transistor. Thus, this active region can be provided in a simple linear shape, so that all active regions including those other than this active region can be simply linearly shaped.
The gate width of the aforementioned load MOS transistor may be rendered smaller than the gate width of the access MOS transistor and that of the driver MOS transistor or larger than the gate width of the access MOS transistor and that of the driver MOS transistor, or may be equalized with the gate width of the access MOS transistor and that of the driver MOS transistor.
A first separation width (corresponding to a separation width SA in FIG. 1) between access MOS transistors adjacent to each other along the gate width direction of the aforementioned access MOS transistor, a second separation width (corresponding to a separation width SD in FIG. 1) between driver MOS transistors adjacent to each other along the gate width direction of the driver MOS transistor and a third separation width (corresponding to a separation width SL1 in FIG. 1) between load MOS transistors adjacent to each other along the gate width direction of the load MOS transistor may be equalized with each other.
A fourth separation width (corresponding to a separation width SL2 in FIG. 1) between load MOS transistors adjacent to each other along the gate length direction of the load MOS transistor and the aforementioned first, second and third separation widths may be equalized with each other.
A fifth separation width (corresponding to a separation width SLD in FIG. 1) between the load MOS transistor and the driver MOS transistor adjacent to each other along the gate width direction of the aforementioned load MOS transistor, a sixth separation width (corresponding to a separation width SAL in FIG. 1) between the load MOS transistor and the access MOS transistor adjacent to each other along the gate width direction of the access MOS transistor and the aforementioned first, second and third separation widths may be equalized with each other.
The aforementioned static semiconductor memory device further comprises an active region including a source region and a drain region of the load MOS transistor. In this case, the active region is preferably continuously formed between load MOS transistors adjacent to each other along the gate length direction of the load MOS transistor, and an isolation element is preferably formed on the active region located between the load MOS transistors. The isolation element may include a MOS transistor having a higher threshold voltage than the load MOS transistor.
A trench isolation region may be provided to divide the active region located between the load MOS transistors adjacent to each other along the gate length direction of the load MOS transistor. This trench isolation region is preferably prepared through an active region forming pattern obtained by forming an active region forming base pattern consisting of a simple line-and-space pattern, for example, and thereafter forming a trench forming hole pattern on a prescribed position of the base pattern.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.